1. Field of the Invention
The present invention relates to a static semiconductor memory and, in particular, an internal synchronization type static RAM which includes a circuit for separately generating a bit line equalize signal and bit line precharge signal and separately supplying them to the corresponding bit lines for a memory cell and a circuit for preventing an entry of write data from being made, for a predetermined period of time, by a resetting operation and ensures an adequate operation margin against a write recovery time.
2. Description of the Related Art
Of those memories generally called a random access memory (RAM), a static RAM (SRAM) is known which employs memory cells composed of a flip-flop circuit of two cross-connected inverters.
This type of SRAM is disclosed in MASATAKA MATSUI U.S. Pat. No. 4,916,668 entitled "INTERNAL SYNCHRONIZATION TYPE MOS SRAM WITH ADDRESS TRANSITION DETECTING CIRCUIT" issued Apr. 10, 1990 and assigned to Kabushiki Kaisha Toshiba, that is, the same assignee as that of the present invention. The SRAM is also disclosed in "1985 International Solid-State Circuits Conference Digest OF TECHNICAL Papers pp 64, 65A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier" Kiyofumi Ochii et al.
In the conventional SRAM, a precharge and equalize signals generating circuit is connected to memory cells to generate a precharge signal for precharging the corresponding memory cell and an equalize signal for equalizing the corresponding memory cell. In this SRAM, an ideal design is sought to achieve a write recovery time TWR=0. In this state, the precharge/equalize signal is generated to hold the bit line potential at an intermediate potential level. At this time, the internal write signal is disabled to place a corresponding write transistor pair in the OFF state. It is thus possible to prevent a data write error.
In the real SRAM, an operation margin which establishes a write recovery time TWR.ltoreq.0 is needed to ensure the write recovery time TWR=0. However, if an address variation occurs before a return of the write signal back to a disabled level, the internal write signal is held in the enabled state and there is a possibility that error data will be written into that memory cell by an address of the next cycle.
That is, since, even in the event of a transition to an address of the next cycle during the data write operation, intermediate potentials appear on the paired bit lines during the generation of a precharge and equalize signals, no write error occurs, but at the completion of the precharge/equalize signal a write error will occur.